The present invention relates generally to the field of performing a quiesce request for a computer system, and more particularly to performing a processor recovery operation during the quiesce request.
During a computing system's operation, a processor or processing core of the computing system may issue a quiesce request to the halt or suspend operation of all other processors or cores of the computing system. A processor or core issues a quiesce request when an instruction requires access to one or more resources of the computing system, where the operation requires the resource to remain unchanged or unaltered during the execution of the operation. In a multi-threaded environment, programs executing on other processors or cores may access and alter the information stored in the resource and therefore are suspended until the initiating processor of the quiesce request performs the operation which required the quiesce state. During a processor's operation, the processor or core may determine that a recovery of the processor or core is to be performed. For example, a parity error may be detected within the resources of the processor or core such as the processor or core's cache. As such, the processor performs a recovery operation to correct the detected error. The processor is unable to send or receive information to and from the computing system during recovery. Therefore, a processor or core would not receive information pertaining to the status of a quiesce state of the computing system during the processor's recovery.